makefile - Make computes wildcard too early? -

I have a lower file, less or more, the following structure that compiles the C ++ source code:

  .phone: all of all: compile_obj_files my_binary # This rule generates object files it works fine afaik .PHONY: compile_obj_files compile_obj_files: $ (create) --file = child.makefile # my_binary one There is a real binary file that I want to create. My_binary: $ (wildcard * o) $ (CC) $ (wildcard * o) -o my_binary  

generates all the object files on the run for the first time, but $ (Wildcard * OO) returned an empty list, in the second race nothing was compiled as expected, and $ (wildcard * o) actually all the objects Returned files. It looks like $ (Wildcard * .o) is executed before all the objects of the file, despite the fact that my_binary rule compile_obj_files . I look helpless on this script without any idea what is wrong (something should be silly). Can you think anything

you should not really use $ (wildcard ...) Inside the rules, but do something like this

  MYSRC: = $ (Wildcard * .c) MYOBJ: = $ (patsubst% .c,% .o, $ (MYSRC))% .o :% .c $ (CC) -C $ & lt; In this way, you know that  MYSRC  and  - o $ @ my_binary: $ (MYOBJ) $ (CC) $ ^ -o $ @  

Match MYOBJ to indicate the target target file name of the current target to indicate the dependence of the current target $ & lt; Also note the use of and $ @ .

Edit: To include the all object files in the link step, click $ & lt; was changed to $ ^ not only the last one

Edit: If you source source names from child.makefile If you do not want to remove, then you should be able to do something like this:

  OBJS  is the code when my code is my_binary  in this way, you are clearly in two steps. Split the construction, and the list of object files is read before it is made.