Neural Network simulator in FPGA? -


To learn FPGA programming, I am planning to create a simple neural network in FPGA (because it is widely parallel, it is one of the few things where an FPGA implementation can have the chance to be faster than the CPU implementation ).

However, I'm familiar with C programming (10+ years). I do not believe so much about FPGA development material

>

Most efforts to build a 'literal' nerve network on an FPGA hit the boundary of the road very quickly, P & amp; You can get a few hundred cells before pulling the R. It takes more time to finish than your problem; Most of the research in NN & amp; amp; The FPGA takes this approach, focusing on at least 'node' implementation and suggesting scaling is no longer trivial.

The method of shaping exactly the working nervous system is to use FPGA to create a dedicated nervous network, get your initial node value in number crunching machine memory chip, your next timestamp results For a second memory chip, and the third area to store your connectivity weight. Pumping node values ​​and connection data using techniques to keep memory buses saturated (order node load by CAS line, reading-ahead using pipelines). It passes in a large number compared to the previous dataset because you add loads with the previous values, they run through the DSP Mac units to evaluate the new node weight, once again after evaluating all the connections, the result is in the memory area Get out in After you have completed the entire timestamp, reverse the flow direction so that the next timestep is written back to the original storage area.


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